Bilayer Taper Etching of Field Oxides and Passivation Layers

Abstract

As geometries and design rules become more stringent for multilayer devices, precise taper control is essential to insure high reliability products. A bilayer process appears to provide precise taper control and the ability to adjust the taper angle as various IC designs may require. The taper control layer of a bilayer process minimizes the effect of the photoresist‐oxide interface properties on the tapering process. Control of the taper is determined by the etch ratio of the underlying layer's etch rate to the taper control layer's etch rate. Examples presented here show that thermal can be tapered with control layers of CVD and 6% densified PSG can be tapered with an undensified PSG layer of similar phosphorus concentration. Optimum control layer thickness ranges from 500 to 1000Å. Taper angles are relatively insensitive to etch temperature and buffer composition changes for buffered etchants. Taper slopes were estimated by a combination of Tencor Alpha‐Step profilometry or interference fringes obtained from optical microscopy. SEM analysis was used to verify these results.