Bias-stress-induced creation and removal of dangling-bond states in amorphous silicon thin-film transistors

Abstract

We report on the threshold voltage shift in amorphous silicon thin-film transistors, subjected to a gate bias for a prolonged period of time (bias stress). For transistors made with a silicon nitride gate insulator, the threshold voltage shift for low positive bias is due to dangling-bond-state creation in the amorphous silicon layer. For low negative bias, the threshold voltage shift is due to the bias-stress-induced removal of dangling-bond states. These results are contrasted with previously published results for oxide transistors, but both results are consistent with a defect pool model for the dangling-bond states. The difference for oxide and nitride transistors is due to a different zero-bias Fermi energy position at the interface. For nitride transistors at much larger applied bias, the dominant mechanism changes and the threshold voltage shift is dominated by charge trapping in the gate dielectric. This is found for both large negative and large positive bias.