Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs

Abstract

In this work, the instability of n-channel 4H–SiC double-implanted metal–oxide–semiconductor field-effect-transistors (DMOSFETs) was studied, in terms of threshold-voltage ( V TH) shifts and drain–source current ( I DS) transients, for different gate bias stress durations of range 100–5500 s. At room temperature, for positive gate bias stress, the V TH shift and I DS decay increase with increasing stress time. The V TH shift and the I DS decay were recovered by negative gate bias stress. It is believed that the instability in device behavior during positive gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. Elevated temperature measurements have indicated a decrease in V TH and an increase in I DS with increasing stress time possibly due to mobile positive ions in the gate dielectric.