Abstract
This paper presents a versatile bit-error-rate (BER) testing scheme to characterize the quality of communication interfaces. Traditionally, the presilicon BER is evaluated using time-consuming software simulations. The stand-alone BER test products for postsilicon evaluation are expensive and do not include channel emulators, which are essential to testing the BER under the presence of noise. For both the design and evaluation phases, we present a scheme for BER testing in field-programmable gate arrays (FPGAs) that consists of a BER tester (BERT) core and a novel additive white Gaussian noise (AWGN) generator core. The maximum output value of our AWGN generator is 53, whereas that of the existing solutions is less than 7. Therefore, our generator can better emulate the tail of a Gaussian distribution, which is suitable for exploring applications at very low BERs. We also present a pipelined structure that exploits the central limit theorem for speedups of four or more. Combining a BERT and an AWGN in FPGAs is orders of magnitude more efficient in cost, volume, and energy over the existing similar-speed stand-alone solutions and has a huge speed advantage over software simulations. We demonstrate the applications of our solution through two case studies.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Instrumentation and Measurement
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
