Benchmarking Digital Die-to-Die Channels in 2.5-D and 3-D Heterogeneous Integration Platforms

Abstract

In this paper, compact circuit models and HSPICE simulations are used to benchmark die-to-die communication channels in 2.5-D and 3-D heterogeneous integration platforms. The delay, energy-per-bit, and bandwidth-density of the considered integration platforms are simulated and benchmarked. Compared to other 2.5-D integrated systems with a 1-mm interconnect length, heterogeneous interconnect stitching technology (HIST)-based 2.5-D integration shows a maximum latency and energy reduction of 6.2% and 15.1%, respectively. 3-D ICs show further performance enhancement compared to 2.5-D integration; the link latency and energy are approximately 19.4% and 48.0% smaller than those of HIST (1-mm wire) for through-silicon via (TSV)-based 3-D integration (75-μm TSV height). Next, the impacts of the physical I/O interconnect dimensions and device process technology scaling are evaluated and we observe that advanced process technologies must be integrated with smaller physical I/O dimensions and shorter wire lengths to attain full advantages of scaling. Finally, we consider the thermal impact of dense heterogeneous integration and investigate the thermal and electrical signaling tradeoffs in 2.5-D and 3-D integration.