Behavioral modeling of continuous time ?? modulators

Abstract

A mixed-signal time behavioral model of a time delta-sigma modulator (CT /spl Delta//spl Sigma/) is presented. CT /spl Delta//spl Sigma/ modulators, by their nature, are mixed-signal systems. That fact creates a discontinuity in the traditional IC design flow which assumes that discrete and continuous time domain designs require separate design tools. We present a top level behavioral CT /spl Delta//spl Sigma/ model that can be used within the IC design environment. High speed CT /spl Delta//spl Sigma/ modulators are implemented using both analog and digital subblocks. We created mixed-signal models of the subblocks in order to efficiently perform simulations that accurately reflect circuit behavior in the time domain. The models were built out of primitives available in SPICE and Verilog-A/sup /spl trade//. We present a first order CT low-pass /spl Delta//spl Sigma/ (CTLP /spl Delta//spl Sigma/) as well as a fourth order CT band-pass /spl Delta//spl Sigma/ (CTBP /spl Delta//spl Sigma/) to demonstrate the modeling technique and simulation methodology. We explored the influence of the loop delay and clock jitter on the CT /spl Delta//spl Sigma/ performance.