Abstract
Coordinate rotation digital computer (CORDIC) algorithm has been widely used in modern digital communication systems such as all-digital phase-locked loop, fast Fourier transform and direct digital frequency synthesizers. Precision of the CORDIC algorithm implemented using pipelined architecture has to be guaranteed by increasing the number of iterations, which leads to large delay, excessive consumption of hardware resource and other problems, unfavorable for applications calling for high real-time performance and low power consumption. In this paper, through integrated use of binary to bipolar recoding, angle domain folding, merging iteration and optimized lookup table, an iteration-free CORDIC algorithm was proposed, with which it takes only two clock cycles to get the output, and it enables certain improvements in hardware consumption and output precision when compared with other basic implementation methods.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
