Baud rate pattern-adaptable dual loop clock recovery for high speed serial links

Abstract

We present a novel symbol-spaced (baud-rate) clock-and-data recovery (CDR) architecture for high-speed electrical interconnects. Our architecture incorporates two feedback loops operating off of a single 1-bit sampler (slicer), sampling the difference between the incoming data and an offset voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> at the data symbol rate. One loop adapts the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> and the other loop automatically reacts to adjust the sampling phase. By deploying customized pattern screening functions for generating the error signal feeding the two feedback loops, the CDR jointly optimizes V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> and the sampling phase such that certain target criteria are realized. For example, in one special case, the system can be configured to lock to a sampling phase where pre and post-cursor inter-symbol interference (ISI) taps are equal; similar to a Mueller-Muller (MM) architecture. In other scenarios, the system can be configured to lock to a phase that makes pre-cursor or post-cursor ISI zero. Compared to a conventional MM baud-date CDR architecture, our proposed architecture can lead to more optimized performance tailored to the channel response, and can lock to clock pattern for fast frequency acquisition. Compared to conventional over-sampled CDRs, our architecture can lead to substantially less power by eliminating the need for the generation and distribution of additional clock phases, and the extra crossing (edge) slicers.