A 10 Gb/s receiver with equalizer and on-chip ISI monitor in 0.11 μm CMOS

Abstract

This paper presents a 10 Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 /spl mu/m CMOS. The areas and power consumptions are 47 /spl mu/m/spl times/85 /spl mu/m and 13.2 mW for the equalizer and 145 /spl mu/m/spl times/80 /spl mu/m and 10 mW for the ISI monitor.