(Ba,Sr)TiO3 Thin Films for Dram’s

Abstract

The DRAM (dynamic random access memory) has been the dominant solid state memory since it was patented in 1967 [1] and first mass marketed as a 4 Kb DRAM by Intel Corporation in 1972 [2]. The success of this memory device over its competitors was its simple and small cell design consisting of one transistor and one capacitor (1T-1C) per bit. A schematic diagram of a DRAM cell and array is shown in Figure 1. Data are stored in an array of capacitors at the intersection of columns of bit lines and rows of word lines. Applying a voltage to one row of word lines turns “on” a row of transistors, allowing a row of capacitors to discharge onto their individual bit lines. During a read operation, a “sense amplifier” at the end of each bit line determines if the capacitor was charged 1 or 0 and then rewrites that charge by applying the appropriate voltage prior to the word line turning “off”. Most DRAMs set the value of the ground electrode of the capacitor to half of the operating voltage of the chip (Vcc) and then a 1 or 0 is stored by applying either Vcc or OV to the capacitor. One advantage of this approach is that the voltage across the capacitor is only +/- Vcc/2. The minimum size of the cell capacitance is determined by the bit line capacitance, the leakage current through the transistor and the cell capacitor, and the charge collected from an α-particle traveling in the Si near the transistor. The α-particles are generated from the decay of naturally occurring isotopes such as Ur which are considered to be contaminants. Since the capacitors lose charge, the cells are recharged using a refresh operation; therefore, DRAM is a volatile memory device.