Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Abstract

Wireline communication applications typically require a low-phase-noise wide-tuning-range PLL. While these requirements can be met using traditional charge-pump PLL architectures, a high-performance digital PLL (DPLL)-based solution offers potential advantages in area, testability, and flexibility. Nearly all high-performance DPLL architectures reported in the literature to date (see, e.g., [1–3]) incorporate a time-to-digital converter (TDC) that acts as the loop's PFD. Subject to its quantization limits, a high-resolution TDC generates output signals proportional to the phase error at its input, effectively linearizing the PFD response. It should be noted, however, that reported high-performance TDC-based DPLLs have generally been fractional-N, i.e., not integer-N, synthesizers. In a fractional-N loop, the phase difference between the feedback clock and the reference clock at the PFD input varies significantly, frequently jumping by as much as a full output clock period from one phase comparison to the next. At 10GHz output, this results in a 100ps phase shift, thus making a TDC with resolution on the order of 10 to 20ps adequate to generate multiple quantization levels. In an integer-N case, by contrast, a PLL with 500fs rms jitter at the output and a typical feedback divider value in the range of 16 to 40 would have feedback phase jitter of only 2 to 3.2ps rms . In this low noise situation, a TDC with less than 3.2ps of resolution would act essentially like a bang-bang PFD (BB-PFD). Existing wireline communication PLLs are predominantly integer-N designs with strict system-level requirements on the rms jitter. A DPLL designer targeting these applications, therefore, would have to face the challenging and ever-increasing requirements on TDC resolution, or to find a way of using a BB-PFD.