Abstract
The adoption of digital-to-time converters (DTCs) along with coarse, or even single-bit, time-to-digital converters (TDCs) is known to substantially reduce jitter and power consumption of digital fractional-N PLLs. Beside these advantages, DTC-based PLLs enable an adaptive pre-distortion algorithm which mitigates the nonlinearity of the DTC and the nonlinearity-induced fractional spurs. This paper provides a novel analytical framework of this linearization algorithm and demonstrates a reduction of fractional-N in-band spurs by 25 dB in a 3.6-GHz digital PLL.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.