Abstract
The adoption of digital-to-time converters (DTCs) along with coarse, or even single-bit, time-to-digital converters (TDCs) is known to substantially reduce jitter and power consumption of digital fractional-N PLLs. Beside these advantages, DTC-based PLLs enable an adaptive pre-distortion algorithm which mitigates the nonlinearity of the DTC and the nonlinearity-induced fractional spurs. This paper provides a novel analytical framework of this linearization algorithm and demonstrates a reduction of fractional-N in-band spurs by 25 dB in a 3.6-GHz digital PLL.
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