Bandwidth and power management of glueless 8-socket SPARC T5 system

Abstract

Continuous advancement in multicore and multi-threaded design requires optimized integration of hardware and software to address increasing bandwidth and power management challenges for high-end system designs. The next generation Oracle T-series systems utilizing the SPARC T5 processor address these challenges. These systems scale from one to eight sockets using a 1-hop glueless connection. The processor implements 16 8-threaded cores, an 8MB L3 cache, four on-chip memory controllers and two on-chip PCIE Gen 3 interfaces [1]. The 8-socket system comprises an unprecedented 1024 threads to deliver the highest thread count ever in any T-series system. The fully configured 8-socket T5 system supports DDR3-1066-based memory bandwidth, which reaches over 2.9TB/s, coherence bandwidth of 2+TB/s and PCI Gen 3 bandwidth with 256GB/s to deliver 5+TB/s throughput (Fig. 3.7.1).