4.3 Fine-grained adaptive power management of the SPARC M7 processor

Abstract

The goal of the power management system of Oracle's SPARC M7 CPU [1] is to maximize the performance of commercial, cloud and big-data workloads subject to thermal and electrical constraints in a variety of system environments. Under thermal constraints, the goal is to maintain silicon die temperature within a target limit with a time constant of milliseconds to seconds, and under electrical constraints the current draw on a supply must be maintained below a threshold with a time constant of microseconds. The processor is designed to run a range of commercial workloads, potentially in virtualized environments, resulting in widely varying activity factors across the chip. Thus, the system must implement a fine granularity of control to achieve maximum performance across the entire range of workloads. These challenges are addressed with a number of advances over the previous generation processors [2] by implementing a low-latency on-die hardware power management system comprised of fast, accurate sensor designs (dynamic power meters and thermal sensors), a proportional feedback control system implementing thermal, current and chip power capping algorithms (Fig. 4.3.1), and actuation mechanisms with different latencies and structural granularities. The 32 cores and 64MB L3 cache are organized as 8 SPARC cache clusters (SCCs) each comprising 4 cores and an 8MB L3 Cache partition. Each SCC includes 6 dynamic power meters and 2 temperature sensors. The granularity of actuation for power management includes SCC-level clock cycle skipping, SCC level frequency scaling and voltage scaling for groups of 2 or 4 SCCs, as shown in Fig. 4.3.2. The power management system supports multiple DVFS power domain configurations.