Bandgap modulated phosphorene based gate drain underlap double-gate TFET

Md Abdullah-Al-Kaiser,Dip Joti Paul,Quazi D M Khosru

doi:10.1063/1.5049611

Md Abdullah-Al-Kaiser, Dip Joti Paul + Show 1 more

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https://doi.org/10.1063/1.5049611

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Abstract

In this work, a novel bandgap modulated gate drain underlap (BM-GDU) structure of tunnel-FET exhibiting suppressed ambipolar characteristics and steep SS is proposed by applying layer dependent bandgap and electron affinity property of 2-D material Phosphorene. An artificial hetero-junction between the source and channel region is composed of trilayer and bi-layer Phosphorene respectively without any lattice mismatch. BM-GDU TFET exhibits ON-current ∼100 μA/μm, on-off ratio greater than 109 and average subthreshold swing 28.6 mV/decade for a channel length of 20 nm at VDD of 0.4 V due to its low bandgap at source region than the channel region, larger tunneling window and lower carrier effective mass. Gate drain underlap structure yields ∼10 decades ambipolar suppression than conventional homojunction DG TFET. Performance parameters of our BM-GDU TFET by varying channel length are also studied using our developed self-consistent quantum mechanical transport simulator.

Highlights

Fundamental physical limits for conventional CMOS technology in power efficiency, supply voltage scaling, leakage power dissipation and shrinking channel length have already been reached
We propose a novel structure by applying the layer dependent bandgap and electron affinity property of 2-D material Phosphorene
bandgap modulated gate drain underlap (BM-GDU) tunnel field effect transistor (TFET) reports subthreshold swing (SS) of 28.64 mV/decade which is lower than BM-DG TFET (SS = 40.62 mV/decade)

Summary

Introduction

Fundamental physical limits for conventional CMOS technology in power efficiency, supply voltage scaling, leakage power dissipation and shrinking channel length have already been reached. Boltzmann subthreshold swing limit (60 mV/decade) of traditional CMOS forces researchers to find out the best alternative of CMOS technology for low-power nano-electronics. In this regard, tunnel field effect transistor (TFET) has already demonstrated SS lower than 60 mV/decade and low leakage due to its carrier injection mechanism which is different from conventional CMOS.[1,2,3] Lower SS and low leakage of TFET offer reduction in static and dynamic power dissipation. TFET facilitates further supply voltage reduction as well as channel length scaling for ultra low-power ICs. The main differences of TFET from conventional CMOS technology are carrier injection mechanism and doping type. In recent years 2-D channel materials have drawn quite a lot attention than 3-D channel material for nano devices. 2-D channel materials manifest excellent gate control at lower dimension

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