Balance testing of logic circuits

Abstract

The authors propose a new method for testing logic circuits, termed balance testing, which requires no explicit signatures and is particularly attractive for built-in self-testing. It exploits the balance property possessed by many useful Boolean functions: f(X) is balanced if f(X) = 1 for half its input combinations. The authors analyze balance testing by deriving necessary and sufficient conditions for the detectability of single stuck-line, multiple stuck-line, and bridging faults. These conditions help the designer identify individual faults that remain undetected by balance testing. The analysis also obviates the need for error models that are often difficult to validate. Some feasible design techniques to make logic circuits balance testable are demonstrated.