Background offset mismatch and loop delay mismatch calibration for fixed-window level crossing ADC

Abstract

As an important type of event-driven analog-to-digital converter (ADC), the fixed-window level crossing (LC) ADC is popular for the health internet-of-things (IoT). The size of the voltage window can be affected by the offset and offset mismatch of the two comparators in an LC-ADC, which intuitively decreases its accuracy. However, the analytical foundation and calibration techniques for these mismatches are absent. In this paper, the influence of offset, loop delay, their mismatches on the accuracy evaluation of the LC-ADC is first analyzed. Moreover, since the mismatch information is included in the LC-ADC quantization results, a background calibration technique for the offset mismatch and loop delay mismatch is proposed to correct the size of the voltage window during the signal recovery process for the linearity enhancement. Furthermore, three different interpolation methods for data recovery of the non-uniform sampling ADCs are theoretically analyzed and compared based on an 8-bit LC-ADC design in a standard 0.18-μm CMOS process. Post-simulation results show that with the nearest interpolation, the cubic polynomial interpolation, and the cubic spline interpolation, the proposed calibration technique can the improve effective number of bits (ENOB) of the LC-ADC from 6.92-bit, 8.17-bit, 9.99-bit to 7.76-bit, 9.30-bit, 13.03-bit, respectively.