Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration

Abstract

The manufacturers of high-performance logic have been ardent champions of Moore's Law, which has resulted in exponential increase in aerial transistor density to 100 million transistors per square millimeter of silicon real estate. However, it is the memory chip makers who have taken the first step toward escaping the confines of scaling within the horizontal plane and have embraced the vertical or the third dimension. The dynamic random access memory manufacturers have adopted stacked capacitors that tower above the silicon plane that hosts the access and peripheral transistors, whereas the nand flash memory technologists can stack 128 layers of charge trap flash cells on top of each other in a monolithic fashion. To enable monolithic three-dimensional (M3D) integration of high-performance logic, one needs to solve the fundamental challenge of low temperature (<400 °C) in situ synthesis of high mobility n-type and p-type semiconductor thin films that can be utilized for fabrication of back-end-of-line (BEOL) compatible complementary MOS transistors under the constraint of limited thermal budget. This article discusses recent progress in the selection and optimization of semiconductor materials for BEOL compatible transistors to enable sequential M3D integration for a range of applications.