Abstract
Diamond Schottky barrier diodes (SBDs) are promising candidates for high current operation. Towards achieving this, the device series resistance (Rs) has to be manipulated carefully, and the parasitic resistance [R(p+)] originating from the p+ layer of the diamond SBDs has a significant influence in constituting the device Rs. For the first time, Kumaresan et al. (see the article on pp. 1997-2001) carried out a systematic analysis of the parasitic resistance of pseudo-vertical type diamond SBDs, and for this the authors designed an elegant structure, as shown in the cover image at top. The left bottom image is a curve fitting analysis result of device Rs which reveals the significance of parasitic resistance on device Rs, and the right bottom image reveals that the parasitic resistance from p+ layer can be engineered by varying its thickness suitably. This study paves a way towards designing the p+ layer thickness for achieving a high current transport of the fabricated device, by means of minimizing the parasitic resistance of the p+ layer.
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