Abstract
We report on the impact of source/drain (S/D) metal (molybdenum) etch and the final passivation (SiO2) layer on the bias-stress stability of back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). It is observed that the BCE configurations TFTs suffer poor bias-stability in comparison to etch-stop-layer (ESL) TFTs. By analysis with transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS), as well as by a comparative analysis of contacts formed by other metals, we infer that this poor bias-stability for BCE transistors having Mo S/D contacts is associated with contamination of the back channel interface, which occurs by Mo-containing deposits on the back channel during the final plasma process of the physical vapor deposited SiO2 passivation.
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