Abstract
Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often suggests employing approximate computing to improve the energy-efficiency, performance, and area of floating-point multipliers. Prior work has shown that employing hardware-oriented approximation for computing the mantissa product may result in significant system energy reduction at the cost of an acceptable computational error. This article examines the design of an approximate comparator used for preforming mantissa products in the floating-point multipliers. First, we illustrate the use of exact comparators for enhancing power, area, and delay of floating-point multipliers. Then, we explore the design space of approximate comparators for designing efficient approximate comparator-enabled multipliers (AxCEM). Our simulation results indicate that the proposed architecture can achieve a 66% reduction in power dissipation, another 66% reduction in die-area, and a 71% decrease in delay. As compared with the state-of-the-art approximate floating-point multipliers, the accuracy loss in DNN applications due to the proposed AxCEM is less than 0.06%.
Highlights
Energy consumption is the main issue in VLSI design, especially in nano-scale devices, while continuing demand for higher computational power is increasing for emerging applications
Approximation methods are applied in different levels of designs, and they provide a trade-off between the required system parameters such as power consumption, delay, and accuracy which is presented by several metrics as the Mean Error Distance (MED), Mean Squared Error (MSE), and Mean Relative Error Distance (MRED) [2]
We propose two novel designs called AxCEM1 and AxCEM2 by performing gate-level logic simplification to Comparator-Enabled Multiplier (CEM). (3) we show that the proposed designs, when employed in deep neural networks (DNNs) applications, demonstrate less than 0.06% accuracy loss, while they show better performance compared to the state-of-the-art approximate floating-point multipliers
Summary
Energy consumption is the main issue in VLSI design, especially in nano-scale devices, while continuing demand for higher computational power is increasing for emerging applications. Research shows that accurate computing units are not necessary for many applications such as data mining and multimedia applications. They can tolerate imprecision [1]. Floating-point multiplication is the main component in many applications such as DSPs, multimedia, and it may cause considerable delay and power consumption. In floating-point multiplications, the most resource-intensive portion is the mantissa product computation unit, consuming almost 80% of the total system energy [3]. The 52 least significant bit, A51, ..., A0, show the mantissae which is a number between 1 and 2 (note that the 1 is implicit and the 52 LSB bits, store a fractional value)
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