Avoiding secondary cache conflict misses in a real‐time system

Abstract

The performance of real-time systems (RTS) with large-scale direct-mapped secondary caches is largely dependent on the state of physical memory page allocation when the cache hit rate is not high. To overcome that problem, the author proposes two optimization methods for minimizing secondary cache conflict misses, assuming an RTS for which page allocation is not performed during a service, and evaluates these methods by simulations based on actual RTS trace data. The evaluations show a performance improvement of from 30% to 100% for secondary cache capacities ranging from 128 KB to 1 MB in a system that employs the MIPS R4000 processor. © 1998 Scripta Technica, Syst Comp Jpn, 29(4): 43–59, 1998