Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms

Abstract

The work, presented in this paper has been carried out within an EU-funded project with the name EXTRA, aimed at creating an environment to generate, configure and evaluate user-customizable Coarse-Grained Reconfigurable Array (CGRA) architectures, called VCGRA. The tools provide a fully automatic development and evaluation platform for a VCGRA architecture including synthesis and execution of the VCGRA with its corresponding hardware configuration and the required interfaces on an FPGA platform. Furthermore, it also provides the necessary software modules for data transmission between the processing system (PS) and the VCGRA on reconfigurable hardware. In this paper, the part of the “VCGRA Toolflow” which is responsible to provide the generation of the VCGRA hardware’s FPGA-bitstream from a specification is discussed. Especially the generation of the VCGRA hardware, the automatic creation of the required interfaces and the evaluation of the improvements are presented. The toolflow is planned to be an open source project, providing hardware developers with a framework to create extensions for the VCGRA architecture, and to make them accessible for software developers. Many aspects of the hardware can be customized, including the functions provided by the Processing Elements and the communication infrastructure as well as the target platform integration. Furthermore, software developers from the EDA domain are enabled to provide, integrate and evaluate algorithms for application mapping.