Automatic layout optimization of DMOS transistors for lower peak temperatures and increased energy capability

Abstract

DMOS transistors often suffer from substantial self-heating during high power dissipation, which can lead to thermal destruction if the device temperature reaches excessive values. A successfully demonstrated method to reduce the peak temperature is the redistribution of power dissipation density from the hotter to the cooler device areas by careful layout modification. However, this is very tedious and time-consuming if complex-shaped devices as often found in industrial applications are considered. This paper presents an approach for fully automatic layout optimization which requires only a few hours processing time. The approach is applied to complex-shaped test structures which are investigated by measurements and electro-thermal simulations. Results show a significantly lower peak temperature and an energy capability gain of 84%, offering potential for a 18 % size reduction of active area.