A simple approach to reduce peak temperatures in integrated and discrete power mosfets

Abstract

DMOS transistors are often subject to large power dissipation and thus substantial self-heating. This can lead to extremely high device temperatures, thermal runaway, and device failure. Because of this, the safe operating area of the DMOS is limited by its peak temperature. Therefore, it has been suggested to lower the peak temperature by shifting the heat generation from the hotter to the cooler parts of the device. In this paper a simple approach to redistribute the power dissipation density in DMOS transistors will be presented that can be used to reduce the peak temperature significantly. The proposed approach can easily be applied to integrated and discrete power MOSFETs. Layout modifications are usually sufficient, no process changes are required. The impact on the electrical characteristics of the DMOS will be evaluated and explained. The presented approach can effectively lower the peak temperature in typical DMOS transistors as will be demonstrated by measurements and numerical simulations.