Abstract
Inherent high switching frequency ability makes silicon carbide Metal-Oxide-Semiconductor Field-Effect transistor more sensitive to the parasitics and noise in the circuit. The layout of gate driver has a crucial influence on the parasitics, hereby the propagation delay and rise/fall time of the driving signal which is among the dominant factors to determine the switching performance of power device. In this paper, an automatic layout design based on genetic algorithm for gate driver is developed. Detailed description of the gate driver layout design is given. Experimental results verified the effectiveness of the design procedure. The speed and validity of the approach make it a valuable tool, and it can be extended to power circuit design, even power converter design easily.
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