Automatic correction of logic bugs in hardware design: Partial logic synthesis

Abstract

Here we consider automatic logic debugging techniques given buggy portions of the incorrect designs. First we consider the logical bugs which can be corrected by only changing types of the gates, i.e., no changes in topology of the circuit in the buggy circuit. This logic correction problem can be formulated as a Quantified Boolean Formula problem by exchanging the buggy gates with LUTs (Look up Table). The generated QBF problems can be efficiently solved by repeatedly applying SAT solvers, and circuits having more than 100,000 gates can be processed. With the evaluation using real life bugs in industrial designs, however, in significantly many cases, not only types of gates but also topologies of circuits must be changed in order to correct the bugs. LUT based formulation cannot be applied directly if inputs to the gate may change. So a new formulation which can search for appropriate signals as the inputs of the target gate is presented. The conditions for the existence of appropriate inputs to the gate have been formulated as a SAT problem. After identifying the inputs to the gate, the LUT based technique can be applied to determine the type of the gate. In most cases, automatic correction of logic bugs can be realized with this approach, and experimental studies show circuits having more than 100,000 gates can be processed. Also, as logic debugging problems are essentially the same as Engineering Change Order (ECO) problems, applications of the presented methods to the accommodation of various small design changes when developing complicated designs, such as high performance computing systems with FPGA, are discussed.