Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism

Abstract

Content addressable memory (CAM) is widely used in many applications, especially for those applications needing fast memory access. However, due to the parallel comparison feature and the frequent precharge/discharge of match-lines, the power consumption of CAM is considerable. In this paper, a fast and automatic charge balancing CAM architecture is proposed to control the voltage swing of match-lines so that the huge power consumption of CAM can be reduced. In the proposed design, the complementary property of the N-type CAM and the P-type CAM is used to balance the charge of match-lines. Especially, no specific sense amplifier is needed to detect the match status of match-lines. For a translation lookaside buffer example with 128 memory entries, the experimental result shows that 25.98% dynamic power and 3.30% leakage power can be reduced by using TSMC 90 nm CMOS process with 1.2 V supply voltage and only 2.23% circuit area is increased when compared with the traditional design.