Abstract
Time-interleaved analog-to-digital converter (TI-ADC) technology can increase the sampling rate without changing resolution. But, the dynamic performance of TI-ADC system is seriously deteriorated by channel mismatches. Under the condition of large bandwidth, gain mismatch and timing mismatch vary with the frequency, which cannot be regarded as fixed values. To improve the dynamic performance of the TI-ADC system, an automatic calibration method of channel mismatches for wideband TI-ADC system is proposed in this article. Frequency-dependent channel mismatches are estimated by the algorithm based on sine fitting, and compensated by the means based on perfect reconstruction. The entire sampling and calculation process is automated and tedious operation is simplified. A 6.8-GS/s 12-bit wideband TI-ADC system is implemented. This sampling system can achieve SNDR (signal-to-noise and distortion ratio) above 49 dB and SFDR (spurious-free dynamic range) above 57 dB for an input signal from 100 MHz to 3300 MHz. The proposed calibration method improves the SNDR over 10 dB and the SFDR over 15 dB. The dynamic performance of the sampling system is close to that of its sub-ADC.
Highlights
The high-speed high-resolution sampling system is the crucial component in wideband digital receivers, measurement instruments, and communication systems [1,2]
Under the condition of large bandwidth, the gain mismatch and timing mismatch of each channel will vary with frequency, which is enough to make the dynamic performance of the sampling system deteriorate seriously
TI-analog-to-digital converters (ADCs) system designed in Section 3 is used for testing
Summary
The high-speed high-resolution sampling system is the crucial component in wideband digital receivers, measurement instruments, and communication systems [1,2]. The performance of the sampling system is mainly determined by analog-to-digital converters (ADCs), including sampling rate, dynamic performance and full power bandwidth. The contradiction between high sampling rate and high resolution restricts the development of ADCs [3]. TI-ADC technology can effectively solve this problem. Several ADCs with lower sampling rate are used to acquire the signal in parallel at the same clock frequency but different clock phases [4,5,6,7]. The sampling sequences of sub-ADCs are combined as the output of the system to increase the sampling rate.
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