Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

Abstract

The three-dimensional (3D) chip stacking LSI technology under development in Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology for realizing high-density and high-speed transmission, and superfine flip-chip bonding technologies utilizing 20-µm-pitch micro bumps on Cu through hole electrodes are substantial technologies. There are two key technical issues involved in realizing the 3D chip stacking LSI. One is the provision of the sufficient interconnections, which have low resistivity and which are absolutely connected. Another is the reduction of the thermal stress of the micro bumps by providing encapsulated resin between devices. Regarding the metallurgically stable and low electrical resistance interconnections, electroplated Au bump bonding in 20-µm-pitch by thermo compression bonding process was evaluated on the chip-on-chip(COC) structure. First, the softening of the Au bump by annealing was confirmed, and was expected to decrease the bonding stress of the under bump structure. Second, the lower limit bonding conditions were confirmed to be a bonding force of 24.5 N at 350°C, and the electrical resistance was confirmed to be stable at about 0.55 Ω. The mechanism of Au–Au thermo compression bonding with the solid phase diffusion across the boundary was confirmed. Finally, the life of the 20-µm-pitch interconnection with the underfillresin containing the hyperfine filler particles under temperature cycling tests (TCT) was more than 1000 cycles, which is an acceptable level for a semiconductor package. This research will enable the realization of 3D chip stacking LSI in the near future which features scalability and high performance. The subjects are the verification of the appropriate bump dimensions in order to further improve the reliability and the realization of the interconnection reliability on 3D chip stacking LSI.