At-speed interconnect test and diagnosis of external memories on a system

Abstract

This work presents a built-in self test (BIST) implementation for external memories like DDR (double data rate), double DDR, QDR (quad data rate) SRAM, DDR FCRAM (fast cycle RAM), and RLDRAM (reduced latency DRAM). We utilize the memory controller in the functional block to design the BIST so that the BIST design can be simplified and executed at the functional speed. However, there are many different types of the memory controllers depending on the types of external memories, functional interface protocols, and implementation methodologies. In order to support the various memory controllers, we defined the latency of the memory controllers and classified them into three different categories: fixed latency, handshake, and both fixed latency, and handshake memory controllers. With these three models, we developed a general BIST architecture to support different types of memory controllers. During the boundary-scan driven BIST operation in the board and the system-level test and diagnosis, system clock, system hard reset, soft reset, and other programmable features were considered carefully to make the BIST operate properly. This work also presents a unique way of utilizing special BIST functions during the board and system level test, and also during the system mission operation.