ATPG Algorithm for Crosstalk Delay Faults of High-Speed Interconnection Circuits

Abstract

With the use of ultra-deep submicron technologies, crosstalk has become one of the major causes of failure of signal integrity (SI) in high-speed circuits. Logic faults and time delays in high-speed circuits happen when crosstalk becomes severe, which leads to serious problems during the design verification and test phases in high-speed circuits. In this paper, a vector generation fault test algorithm for crosstalk delay based on the maximum aggressor model and waveform sensitization is proposed for analyzing the four types of crosstalk delay fault in high-speed interconnection circuits; in addition, by improving the traditional FAN algorithm, the proposed algorithm designates a victim line and maximally activates the corresponding aggressive line so as to generate the maximum access delay in a high-speed interconnection circuit induced in a worst-case scenario. In this algorithm, both the gate delay and the line delay are taken into consideration in high-speed interconnection circuits, and two strategies, including static priority and dynamic priority, are examined to achieve a more efficient delay test. The tests were verified in a standard C17 circuit, and the results show that the test vectors for crosstalk delay faults in high-speed circuits can be detected by the proposed algorithm.