Atomic-Layer Deposited High-k/III-V Metal-Oxide-Semiconductor Devices and Correlated Empirical Model

Abstract

Si CMOS scaling is reaching its physical limit at the 15 nm technology node and beyond. III-V compound semiconductor is one of the leading candidates to replace main-stream Si as n-channel material due its much higher electron mobility. Lacking a suitable gate insulator, practical III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) remain all but a dream for more than four decades. The physics and chemistry of III-V compound semiconductor surfaces or interfaces are problems so complex that even after enormous research efforts understanding is still limited. Most of the research is focused on surface pretreatments, oxide formation and dielectric materials. Less attention is given to the III-V substrate itself. In this chapter, the history and present status of III-V MOSFET research is briefly reviewed. An empirical model for high-k/III-V interfaces is proposed based on the experimental works we performed on III-V MOSFETs using ex-situ atomic-layer-deposited high-k dielectrics and also reported works in the literature using in-situ molecular beam expitaxy grown Ga2O3(Gd2O3) as gate dielectric. The results show that physics related to III-V substrates is as important as surface chemistry and gate oxide properties for realizing high-performance III-V MOSFETs. The central concept of this empirical model is that the band alignment between trap neutral level (E0) and conduction band minimum (CBM) or valence band maximum (VBM) and the magnitude of interface trap density governs the device performance of inversion-mode III-V MOSFETs.