Atomic-scale Dopant Integration During CMOS Device Fabrication

Abstract

As CMOS device dimensions shrink and reach scaling limits, atomic layer-based processing has opened new routes for device fabrication and varied device physics. Atomic precision advanced manufacturing (APAM) for precise placement of dopants in Si either as individual atoms, scanning tunneling microscope (STM)-patterned lines, or as sheets of dopants (a delta layer) opens the opportunity to precisely engineer electronic structure and achieve doping above the traditional solubility limit [1]. APAM processing can complement traditional CMOS devices, modifying or augmenting chips including standard integrated circuits, and here we demonstrate a direct CMOS-integrated process flow for APAM processing.During APAM processing, a clean Si surface is exposed to vapor-phase dopant precursors such as phosphine which adsorb on exposed dangling Si bonds, followed by a thin Si cap. Traditionally, the surface preparation involves flash anneals near 1200 °C to achieve a clean, reconstructed Si surface as well as processing in ultrahigh vacuum for the doping and capping. Atomic-precision patterning is achieved with hydrogen termination then STM-based removal of H using the tip to reach pre-implanted contacts [2], though recent efforts have shown delta layer patterning without the STM using photothermal desorption of the H [3]. The high-temperature surface preparation is incompatible with CMOS process flows, but efforts to reduce the temperature have shown that temperatures of 800 °C or below may be sufficient to produce a clean Si surface [2,4].For direct integration of APAM structures in a CMOS flow, the middle-of-line processing near CMOS contact formation is a natural insertion point, when the device Si is accessible but the transistors’ high-temperature gate and dopant activation steps are finished. We estimate that APAM processing requires temperatures of 400-800 °C for surface preparation, but after APAM processing the devices should stay below about 600 °C to avoid dopant diffusion. By doing APAM processing before metal (copper or aluminum) deposition, the low 500-600 °C limit for MEMS-on-CMOS processing may be avoided [5].As a test platform, custom CMOS devices were fabricated in Sandia’s fab using the 0.35-micron node, including both discrete transistors and simple circuits such as gates and ring oscillators. Specialized cells in the layout enable the demonstration of APAM doping integrated with CMOS elements, with minimal changes to the CMOS flow and masks. After completing gate formation, the wafers are pulled near the contact module for UHV APAM processing, then finished with metallization in a separate fab to do electrical testing.Initial tests subjecting the CMOS chips to surface preparation techniques used for APAM processing show that the CMOS circuits can survive gentle flash anneals and sputter cleans, even when silicide and tungsten contacts are already in place. More in-depth rapid thermal anneal (RTA) studies of the chips’ thermal budget reveal degradation in drive currents and threshold voltages in n-channel devices starting about 600 °C, but switching operation is maintained through 800 °C where the tungsten contacts begin to severely degrade. Current work is ongoing to process samples without tungsten contacts already in place and to achieve delta layer doping on these chips. Our goal is to demonstrate atomic layer doping directly integrated with a CMOS process flow.In summary, atomic-precision device doping is integrated with a standard CMOS process flow, with the thermal budget of both the APAM and CMOS elements determining the fab requirements. If silicide and tungsten contacts are in place, the Si surface preparation techniques are limited to a temperature of about 600 °C which should be compatible with low-temperature options such as Ne sputtering and gentle anneals.SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.[1] B. Weber et al., Science 335, 64 (2012).[2] D. R. Ward et al., Appl. Phys. Lett. 111, 193101 (2017).[3] A. M. Katzenmeyer et al., J. Micro/Nanopattern. Mats. Metro. 20, 014901 (2021).[4] T. Skeren et al., Nanotechnology 29, 435302 (2018).[5] H. Takeuchi et al., IEEE Transactions on Electron Devices 52, 2081 (2005).