Abstract
The real-time operation of the ATLAS dataflow system is highly dependent on the performance of the gigabit Ethernet network interconnecting its components (ap800 end nodes). After examining the functional and performance requirements of the network, several design alternatives (with respect to traffic repartition on core devices and available concentration technologies) are presented and analyzed. We introduce the use of 10 gigabit Ethernet as a flexible and simple technology for concentrating traffic. Network testing equipment as well as discrete model simulations is used to assess the performance of various implementation options. Based on performance, fault tolerance and flexibility considerations a preferred architecture is proposed for implementation
Highlights
The ATLAS TDAQ (Trigger and Data Acquisition) system relies on a three layer trigger to reduce the initial 40 MHz event rate to 200 Hz, before transferring the event data to mass storage
Both technology and our understanding of the TDAQ system have evolved since the initial network design [2]. 10 Gigabit Ethernet (10GE) is well suited for traffic aggregation and is competitively priced
ARCHITECTURE UPGRADE PROPOSAL Fig. 6 depicts the architecture we propose for implementation: the network core is distributed over two large switches, each of them handling a mixture of LVL2 and event builder (EB) traffic; a separate central control switch is used to aggregate the control traffic, while the LVL2 processing units are concentrated using 10GE concatenation
Summary
Abstract— The real-time operation of the ATLAS DataFlow system is highly dependent on the performance of the Gigabit Ethernet network interconnecting its components (¥ 800 end nodes). After examining the functional and performance requirements of the network, several design alternatives (with respect to traffic repartition on core devices and available concentration technologies) are presented and analyzed. We introduce the use of 10 Gigabit Ethernet as a flexible and simple technology for concentrating traffic. Network testing equipment as well as discrete model simulations are used to assess the performance of various implementation options. Fault tolerance and flexibility considerations a preferred architecture is proposed for implementation. After performing the level two rejection, full events are sent further to the Event Filter at approximately 3.5 kHz
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