Asynchronous sampling of an active non‐synchronised time‐to‐digital converter

Abstract

An architecture for a non-synchronised time-to-digital converter is presented. It makes use of a ring oscillator and a coarse counter for an increased dynamic range. This work aims to enable multiple samples of the converter's state to be acquired asynchronously during one run without having to reset it. Such architecture is useful in applications where multiple timing values are required from a single circuit. In this scenario such architecture suffers from a timing violation when both the sampling and counter clock edges happen concurrently, thus sampling the incorrect state. A solution is proposed, and an example of this implementation is also given.