Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

Abstract

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.