Asymmetric U-Shaped-Gated TFET for Low-Power Ana–Digi Applications at Sub-7-nm Technology Node: A Simulation-Based Optimization Study

Abstract

In this article, for the first time, an asymmetric U-shaped-gated tunnel FET (AU-TFET), with a unique vertical channel epilayer, at sub-7-nm technology node, has been proposed and investigated for its suitability to be a universal device. After validating the simulation scheme with the experimental results of fabricated TFET devices, the impact of thickness of the said epilayer ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {epi}}$ </tex-math></inline-formula> ), on device performance, has been thoroughly investigated in terms of a variety of performance metrics, both in analog and digital (Ana–Digi) domains. To increase the vitality of the work, the device-level analysis is stretched to the circuit level. The impact on the inverter performance, both in Ana–Digi domains, in terms of fundamental circuit performance parameters, viz., dc gain, short-circuit power dissipation during switching, noise margin (NM), and so on, has been studied, and ultimately, the most optimized TFET structure, in each domain, has been identified. Finally, in this whole device/circuit co-analysis, after summing up all the performance metrics in both the domains while looking for meeting the low-power (LP) requirements (following the goals, as applicable, of international roadmaps), altogether, we have found that AU-TFET with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {epi}} $ </tex-math></inline-formula> = 6 nm could be considered as the ultimate optimized universal LP Ana–Digi TFET structure.