Abstract
In the present work, a two-dimensional analytical model for novel device architecture, asymmetric gate stack surrounding gate transistor (ASYMGAS SGT) is presented and its effectiveness in suppressing short channel effects and hot carrier effects is investigated. The model is developed by solving the Poisson equation in cylindrical coordinates assuming a parabolic potential profile in the radial direction. Using the model, the expressions for potential and electric field have been obtained and the analysis is extended to obtain the threshold voltage of the device. It is demonstrated that besides improving the short channel immunity and hot carrier reliability, incorporation of asymmetric gate stack architecture also leads to enhanced transport efficiency. In order to verify the model, the analytical results have been compared with the simulated data obtained from device simulator ATLAS and a good agreement is found.
Published Version
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