Assessment of High-k Gate Stack on Sub-10 nm SOI-FinFET for High-Performance Analog and RF Applications Perspective

Abstract

This work explored the performance evaluation of high-k gate stack on the analog and RF figure of merits (FOMs) of 9 nm Silicon-on-Insulator (SOI) FinFET. The results have been observed by replacing high-k dielectric with SiO2 material between gate and fin. The dielectrics investigated in this exploration are Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), Hafnium Dioxide (HfO2), and Aluminium Oxide (Al2O3). The characteristics such as DIBL (Drain Induced Barrier Lowering), SS (Subthreshold Slope), electron mobility, energy band, surface potential and switching ratio (Ion/Ioff) have been performed for the comparison analysis. Further, some important RF figure of merits (FOMs) has been explored and found that the high-k gate stacked SOI-FinFET configuration shows superior RF performance in terms of cut-off frequency (f T) and maximum oscillation frequency (f MAX), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). Thus the implementation of a high-k gate stack, the major limitations of our transistor device such as short channel effects (SCEs), leakage current, and parasitic capacitance have been reduced and pave the way for high switching and RF application.