Assessment and Characterization of Stress Induced by Via-First TSV Technology

Abstract

Through silicon via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress buildup in the silicon substrate that may induce warpage or expansion at the wafer level, strain and crystalline defects in the neighboring silicon of the TSV, and finally can impact the performance and reliability of the CMOS devices as well. Polysilicon, tungsten, and copper are the three main conductors that are currently considered for TSV fabrication. In the first part of this paper, the different factors that contribute to the stress in these three TSV types, including the geometry, the materials, and the process, will be reviewed. After bonding on a temporary carrier and thinning of the substrate to expose the via, the stress built up during the fabrication of the TSV can be also revealed by the expansion of the silicon membrane. We present thermomechanical FEM simulations and compare them with the experimental findings. We also present some characterizations of silicon defects by chemical revelation around the TSV structures. For characterization of the stress in TSV structures, different techniques as EBSD, microRaman, and XRD are presented. Finally, we conclude that with the optimization of some key processing steps, the stress induced in via-first technology may be acceptable for IC integration.