Abstract
In the late years many different interconnection networks have been used with two main tendencies. One is characterized by the use of high-degree routers with long wires while the other uses routers of much smaller degree. The latter rely on two-dimensional mesh and torus topologies with shorter local links. This paper focuses on doubling the degree of common 2D meshes and tori while still preserving an attractive layout for VLSI design. By adding a set of diagonal links in one direction, diagonal networks are obtained. By adding a second set of links, networks of degree eight are built, named king networks . This research presents a comprehensive study of these networks which includes a topological analysis, the proposal of appropriate routing procedures and an empirical evaluation. King networks exhibit a number of attractive characteristics which translate to reduced execution times of parallel applications. For example, the execution times NPB suite are reduced up to a 30 percent. In addition, this work reveals other properties of king networks such as perfect partitioning that deserves further attention for its convenient exploitation in forthcoming high-performance parallel systems.
Highlights
AND RELATED WORKA LTHOUGH a lot of research on interconnection networks has been conducted in the last decades, constant technological changes demand new insights about this key component in modern computers.Many high-performance system networks are based on torus topologies, [1], [2], [3]
With current VLSI technology, the planar substrate in which networks are implemented suggests the use of 2D mesh-like topologies
This has been the case of Tilera [8] and the Intel’s Teraflop research chip [9], with 64 and 80 cores respectively arranged in a 2D mesh
Summary
AND RELATED WORKA LTHOUGH a lot of research on interconnection networks has been conducted in the last decades, constant technological changes demand new insights about this key component in modern computers.Many high-performance system networks are based on torus topologies, [1], [2], [3]. With current VLSI technology, the planar substrate in which networks are implemented suggests the use of 2D mesh-like topologies. This has been the case of Tilera [8] and the Intel’s Teraflop research chip [9], with 64 and 80 cores respectively arranged in a 2D mesh. Multi-level trees are being considered for forthcoming many-core chips using up to thousands of simple execution engines orchestrated by a much smaller number of control engines, [12] Such networks entail the use of long wires in which repeaters and channel pipelining are needed. Forthcoming technologies such as on-chip highspeed signaling and optical communications could favor the use of higher degree on-chip networks
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