Comparison between optimal interconnection network in different 2D and 3D NoC structures

Abstract

The current article studies optimal intercore interconnect network in a NoC structure for 2D and 3D mesh, torus and hypercube topologies. Optimal wire width/spacing is calculated by numerically maximizing bandwidth times the reciprocal delay, which depends on the technology node and hop length. Through 3D integration and increasing tiers, optimal interconnect width and spacing in torus and hypercube topologies will decrease. The core-to-core channel width in all topologies will be obtained by assigning 20% of the power consumption to the routers. By increasing number of cores, channel width will decrease due to reduced power consumption of each core. This is more in hypercube topology, due to the fact that the number of router ports will increase along with an increase in the number of cores. In terms of the worst case delay, mesh topology is worse than the two other topologies. Also it is not scalable due to the increase in the number of cores. In all topologies, power consumption of the chip and the worst case delay will decrease by 3D integration and utilizing more tiers. Mesh and torus topologies make the least and the most use of wiring area, respectively. Bisection bandwidth increases in all topologies by 3D integration.