Assembly reliability improvement of 3D-ICs packaging using pre-stuffed molding material

Abstract

Three-dimensional integrated circuit (3D-IC) packaging has attracted considerable research interest because it allows the integration of heterogeneous functions among stacked chips. The thermal mismatch stresses induced by thermal cycling loads in the interconnects that are composed of a through silicon via (TSV) and microbumps are a serious concern, and thus, a thinner stacked die is required. To shrink the foregoing thickness to less than 10 μm, a novel assembly approach involving the use of pre-stuffed molding material at the wafer-level grinding process is proposed in this study. The assembly results are performed by using a chip-on-wafer module. In addition, the parametric estimation of the induced stress/strain resulting from the geometries of fine-pitch TSVs under temperature cycling loads is also performed by using non-linear finite element analysis. In thick silicon chips, the capability of a stress-release mechanism for the TSV and microbumps depends on the adoption of underfill material and the proper selection of its elastic modulus. By contrast, the non-linear stress/strain at all the interconnects of a 3D-IC package with extremely thin stacked chips decreases due to the excellent flexibility provided by the silicon chip. The results of this study are valuable to the configuration design and demonstrate the feasibility of 3D-IC packages with thin stacked chips assembled through the proposed assembly approach.