Assembly Reflow Process Effect on Interlayer Dielectric Crack and New Finding of Failure Analysis

Abstract

With requirement of superior electrical performance for today's semiconductor devices, ultra-low k (ULK) interlayer dielectric (ILD) materials are used. During back-end flip chip assembly process, due to thermal expansion coefficient (CTE) difference between die and substrate, reflow conducted thermal stress causes ILD crack. In this paper, process reflow condition is investigated to minimize failure rate of ILD crack. The result shows large temperature gradient would cause high failure rate. Longer cooling time is also an effective method to reduced ILD crack failure rate. ILD crack failure is also known as “white spots” which can be detected by C-mode Scanning Acoustic Microscope (CSAM) and confirmed by decapsulation and Focused Ion Beam (FIB). After reflow profile optimization, a new type of CSAM failure “black spots” is observed with the same ILD crack failure mode.