Interlayer dielectric cracking in back end of line (BEOL) stack

Abstract

Copper/low-k dielectrics are used in today's ICs to enhance electrical performance. The low-k interlayer dielectric (ILD) materials have low fracture strength due to the presence of pores or other inclusions to reduce the dielectric constant. During flip-chip assembly, when the die/substrate structure is cooled down from reflow temperature to room temperature, thermo-mechanical strains and stresses develop in the solder bumps. These thermally-induced stresses are due to the differential displacement between the substrate and the die as a result of coefficient of thermal expansion (CTE) mismatch between the die and the substrate. When the thermo-mechanical stresses are high, they can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. This ILD fractures are circular in shape and appear as a white spot in C-mode scanning acoustic microscopy (CSAM) images, and thus, they are often referred to as “white bumps.” In this paper, we present a finite-element-based sub-modeling approach to study the ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, passivation layer, die pad, solder bump, substrate pad, and various layers in the substrate including the trace-pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model” which accounts for the die with its back-end-of-line (BEOL) stack, die pad, passivation layer, solder bump, substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive and interfacial cracks are introduced in the ULK layers present in the BEOL stack, and the energy available for cohesive crack and interfacial crack propagation has been determined. It can be seen that energy available for crack propagation initially increases with crack length, but the energy starts to decay after a particular crack length indicating that the ILD cracking is often confined in the vicinity of one bump. The models can also provide valuable insight into ILD cracking for a wide range of geometry and material parameters. The results from the models have been compared against available experimental cohesive as well as interfacial fracture toughness data for Cu/dielectric material systems.