Assembly and Packaging Enabling System Integration

Abstract

More than Moore is a major trend to tackle the increasing difficulties of traditional Moore's law scaling. System in Package technologies, which allow heterogeneous integration, are appearing in ever more electronic applications. Furthermore we observe merging of silicon wafer technology with assembly and packaging technologies. Today a more coherent development taking into account chip, package, and the board is needed. In this paper we show how assembly and packaging can take up the slack because traditional More Moore downscaling is becoming more difficult. First, we introduce the Thin Small Leadless Package (TSLP) e.g. used in mobile systems. The TSLP is similar to the Quad Flat No-Lead (QFN) package, but thinner and with less parasitics. Second, we introduce wafer level type packages. The limits of standard wafer level packaging in respect to I/O counts pushed the development of the embedded Wafer Level Ball Grid Array (eWLB). We demonstrate the outstanding system integration capabilities of the eWLB including excellent mm-wave performance. For all the above mentioned packages chip and package technologies merge. They are door opener for nanoelectronic devices in respect to energy efficiency, mobility and security.