Abstract
Motion estimation is the most important module in H.264 video encoding algorithm since it offer the best compression ratio compared to intra prediction and entropy encoding. However, using the allowed features for inter prediction such as variable block size matching, multi-reference frames and fractional pel search needs a lot of computation cycles. For this purpose, we propose in this paper an Application Specific Instruction-set Processor (ASIP) solution for implementing inter prediction. An exhaustive full and fractional pel combined with variable block size matching search are used. The solution, implemented in FPGA, offers both performance and flexibility to the user to reconfigure the search algorithm.
Highlights
The fast growth of digital transmission services has created a great interest in digital transmission of image and video signals
We propose in this paper an Application Specific Instruction-set Processor (ASIP) solution for implementing inter prediction
Internal memory is 8 bits width for implementation constraints: since we adopt exhaustive search, the whole reference area is parsed in order to search for the best matching MB; so, if we load more than one pixel from reference area, we will be faced to an alignment problem
Summary
The fast growth of digital transmission services has created a great interest in digital transmission of image and video signals. With the diversity of configurations supported by this standard in terms of resolutions and applications, scalable architectures for video encoders are much appreciated by service providers In this context, neither hardware implementation solutions are efficient since they lack flexibility, nor software solutions present good performance since processors are no longer satisfying the high computational processing tasks [5]. Neither hardware implementation solutions are efficient since they lack flexibility, nor software solutions present good performance since processors are no longer satisfying the high computational processing tasks [5] To meet all these constraints, processor characteristics can be customized to match the application profile. Motion estimation is the most important module in the compression procedure due to its efficiency In this context, some video encoders are using FPGA solutions for implementing motion estimators as hardware accelerators since DSPs cannot handle the processing required by such tasks
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