ASIC implementation of self tuned wave-pipelined circuits

Abstract

Wave-pipelining is a technique used in digital systems to achieve maximal rate operation. Higher operating frequencies can be achieved in wave-pipelined digital circuits, by adjusting the clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual procedures are adopted for the choice of the optimum value of the clock frequency and clock skew between input and output registers of the wave-pipelined circuits. The major contribution of this paper is the proposal for automating the above procedure for the ASIC implementation of wave-pipelined circuits. For the purpose of verification, filters using the distributed arithmetic algorithm are implemented. To test the efficacy of the proposed scheme, filters with different taps are implemented by adopting three schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is observed that the wave-pipelined circuits are 21-29% faster compared to non-pipelined circuits. The pipelined circuits are 22-48% faster compared to wave-pipelined circuits but at the cost of about 18-28% increase in area. At normalized frequency, the pipelined circuits are found to be dissipating 3% more power than the wave-pipelined circuits.