ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining

Abstract

Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. Major contributions of this paper are: proposal for the implementation of one level 2D DWT using lifting scheme by adopting the wave-pipelining technique and proposal for fixing clock frequency and clock skew between the input and output registers of wave-pipelined circuit. For the purpose of evaluating the superiority of the schemes proposed in this paper, the system for the computation of one level 2D DWT is implemented on ASIC using the following techniques: pipelining, non-pipelining and wave-pipelining. From the implementation results, it is observed that the wave pipelined circuit is 1.07 times faster than the non pipelined circuit. The pipelined circuit 1.08 time faster compared to wave pipelined circuit and this is achieved with the increase in area of 1.85 times.